In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have a high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching.
On the other hand, hole mobility on (110) Si is 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobility on (110) Si surfaces is significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Hybrid oriented substrates having planar surfaces with different crystallographic orientation have recently been developed. See, for example, U.S. patent application Ser. No. 10/250,241, filed Jun. 23, 2003 and U.S. patent application Ser. No. 10/696,634, filed Oct. 29, 2003. Additionally, hybrid-orientated metal oxide semiconductor field effect transistors (MOSFETs) have recently demonstrated significantly higher circuit performance at the 90 nm technology node. As discussed above, the electron mobility and hole mobility can be optimized independently by placing the nFET on a (100) surface and the pFET on a (110) surface.
Although hybrid oriented substrates having planar surfaces of different crystal orientation can increase the carrier mobility, further improvement is needed in order to keep the performance scaling as devices are being scaled.
Another means to enhance carrier mobility is to introduce a stress into the channel of the MOSFET. Stress can be introduced into a single crystal oriented substrate by several methods including, for example, forming a stress inducing liner on top of the substrate and around the gate region. In current technologies within the 90 nm mode, strain enhancement for nFETs and pFETs is achieved using a dual nitride liner process. In such a process, a nitride liner of tensile stress is formed about the nFET and a nitride liner of compressive stress is formed about the pFET.
In addition to using two different types of stressed liners to achieve stressed channels in both the pFET and nFET devices, the pFET spacer is typically much wider than the nFET spacer to achieve optimum device parameters, such as, for example, resistance and threshold voltage roll off. When wider pFET spacers are used, the distance of the compressive nitride film to the pFET channel is increased and, as such, there is a diminished strain enhancement on the pFET device. In addition, wider spacers reduce the space between two closely placed pFET devices causing oxide voids in the interconnect dielectric (ILD) that is formed atop the pFET. The ILD voids are later filled with metal during metal contact formation forming metal stringers which may shorten the contacts.
In view of the above, there is still a need for providing a semiconductor structure in which strain enhancement is achieved for both nFET and pFET devices in which the problems of using wider spacers for the pFET device is eliminated.